publications

2024

1. PASTA

   PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs

   Moazin Khatti, Xingyu Tian, Ahmad Sedigh Baroughi, Akhil Raj Baranwal, and 4 more authors

   ACM Trans. Reconfigurable Technol. Syst., Sep 2024

   Abs DOI

   In recent years, the adoption of FPGAs in datacenters has increased, with a growing number of users choosing High-Level Synthesis (HLS) as their preferred programming method. While HLS simplifies FPGA programming, one notable challenge arises when scaling up designs for modern datacenter FPGAs that comprise multiple dies. The extra delays introduced due to die crossings and routing congestion can significantly degrade the frequency of large designs on these FPGA boards. Due to the gap between HLS design and physical design, it is challenging for HLS programmers to analyze and identify the root causes, and fix their HLS design to achieve better timing closure. Recent efforts have aimed to address these issues by employing coarse-grained floorplanning and pipelining strategies on task-parallel HLS designs where multiple tasks run concurrently and communicate through FIFO stream channels. However, many applications are not streaming friendly and many existing accelerator designs heavily rely on buffer channel based communication between tasks.In this work, we take a step further to support a task-parallel programming model where tasks can communicate via both FIFO stream channels and buffer channels. To achieve this goal, we design and implement the PASTA framework, which takes a large task-parallel HLS design as input and automatically generates a high-frequency FPGA accelerator via HLS and physical design co-optimization. Our framework introduces a latency-insensitive buffer channel design, which supports memory partitioning and ping-pong buffering while remaining compatible with vendor HLS tools. On the frontend, we provide an easy-to-use programming model for utilizing the proposed buffer channel; while on the backend, we implement efficient placement and pipelining strategies for the proposed buffer channel. To validate the effectiveness of our framework, we test it on four widely used Rodinia HLS benchmarks and two real-world accelerator designs and show an average frequency improvement of 25%, with peak improvements of up to 89% on AMD/Xilinx Alveo U280 boards compared to Vitis HLS baselines.

2021

1. ReLAccS

   ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems

   Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, and Akash Kumar

   IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Sep 2021

   DOI
2. MemOReL

   MemOReL: A Memory-oriented Optimization Approach to Reinforcement Learning on FPGA-based Embedded Systems

   Siva Satyendra Sahoo, Akhil Raj Baranwal, Salim Ullah, and Akash Kumar

   In Proceedings of the 2021 Great Lakes Symposium on VLSI, Virtual Event, USA, Sep 2021

   Abs DOI

   Reinforcement Learning (RL) represents the machine learning method that has come closest to showing human-like learning. While Deep RL is becoming increasingly popular for complex applications such as AI-based gaming, it has a high implementation cost in terms of both power and latency. Q-Learning, on the other hand, is a much simpler method that makes it more feasible for implementation on resource-constrained embedded systems for control and navigation. However, the optimal policy search in Q-Learning is a compute-intensive and inherently sequential process and a software-only implementation may not be able to satisfy the latency and throughput constraints of such applications. To this end, we propose a novel accelerator design with multiple design trade-offs for implementing Q-Learning on FPGA-based SoCs. Specifically, we analyze the various stages of the Epsilon-Greedy algorithm for RL and propose a novel microarchitecture that reduces the latency by optimizing the memory access during each iteration. Consequently, we present multiple designs that provide varying trade-offs between performance, power dissipation, and resource utilization of the accelerator. With the proposed approach, we report considerable improvement in throughput with lower resource utilization over state-of-the-art design implementations.

3. P4

   Development of Completely Automated Poly Potential Portable Potentiostat

   Akhil Raj Baranwal, Sohan Dudala, Prakash Rewatkar, Jaligam Murali Mohan, and 2 more authors

   ECS Journal of Solid State Science and Technology, Feb 2021

   Abs DOI

   Various research activities related to profiling chemicals employ detection or measurement of the response from a specimen in terms of electric fields or currents. Hence, a portable poly-potential device forms one of the necessary measuring equipment essential to these domains. This work aims to propose a Poly-Potential Portable Potentiostat (P4), that can perform electrochemical analysis of solutions through easily integrable data-acquisition hardware and flexible software post-processing. The P4 device is based on a commercial development board, which provides an analog front-end (AFE) for working with 2-lead and 3-lead amperometric cells. An economical and portable design approach is prioritised while keeping the basic functions of the research-grade commercial instruments. A novel technique of dynamically changing the bias and reference potential is used to achieve a finer resolution, enabling qualitative estimation. P4 works by performing detailed mathematical post-processing on-board and therefore relies on hardware integrity as much as on software flexibility. Calibration of P4 was done using a standardised solution to function independently of any external hardware or software tools. P4 makes electrochemical analysis truly portable in remote or resource-constrained applications.