Akhil R. Baranwal

10817

Applied Sciences Building

Simon Fraser University

Burnaby, British Columbia

Canada, V5A1S6

Namaste! Fellow traveller on this blue orb.
I currently work as a research assistant at HiAccel lab, while enrolled as a MASc student studying Computer Engineering at Simon Fraser University (SFU) and advised by Dr. Zhenman Fang.

My current research interests include characterization of accelerator-rich architectures and systems for ML. Most of my work tightly involves relevant EDA. I think that closing the gap between software-programmers and hardware-designers is as tremendously significant as challenging.
I am also interested in the general study of cognition, sentience and behaviour of the mind, and always open to discuss neuroscience-inspired hardware architecture design.

Before joining HiAccel, I worked at Imagination Technologies as a Design Engineer for uncore IPs of RISC-V based automotive CPUs, and at Micron Technology as a SoC Verification Engineer for UFS storage controllers (ASICs). During my late undergraduate years, I worked as a guest researcher with the Chair for Processor Design, CFAED, while working on accelerator designs for reinforcement learning. Before I dived into computer architecture, I tinkered with electronics and used my degree in Electronics & Instrumentation to make low-budget laboratory equipment - a cheap potentiostat for voltammetry and a spectrophotometer for colorimetry over the visible region. These are Arduino-based designs, firmware for both of these are available as free downloads on my Github. This work was possible because of my engagement with the MMNE Lab.

I received my B.E. in Electronics Engineering in 2020 from BITS Pilani, Hyderabad Campus. Lite.

In my natural habitat, I can be observed staring either into some screen or into some cookware.
It’s possible I’m currenty sipping some variant of tea _(slurp)

news

Sep 02, 2023	I start my research at Hi-Accel Lab.
Aug 07, 2022	Excited to join Imagination Technologies for development of automotive CPUs!
Feb 14, 2022	I tape out the first chip of my career
Sep 15, 2020	I join Micron Technology for development of UFS 4.0 storage controller ASICs.
Jul 30, 2020	I have graduated with Honors from BITS Pilani

latest posts

Jan 23, 2025	2025 already, is it?
Oct 12, 2024	Restarting in 2024
Dec 25, 2021	On Finding Your Zima Blue

publication highlights

ReLAccS

ReLAccS: A Multilevel Approach to Accelerator Design for Reinforcement Learning on FPGA-Based Systems

Akhil Raj Baranwal, Salim Ullah, Siva Satyendra Sahoo, and Akash Kumar

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021

DOI
PASTA

PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs

Moazin Khatti, Xingyu Tian, Ahmad Sedigh Baroughi, Akhil Raj Baranwal, and 4 more authors

ACM Trans. Reconfigurable Technol. Syst., Sep 2024

Abs DOI

In recent years, the adoption of FPGAs in datacenters has increased, with a growing number of users choosing High-Level Synthesis (HLS) as their preferred programming method. While HLS simplifies FPGA programming, one notable challenge arises when scaling up designs for modern datacenter FPGAs that comprise multiple dies. The extra delays introduced due to die crossings and routing congestion can significantly degrade the frequency of large designs on these FPGA boards. Due to the gap between HLS design and physical design, it is challenging for HLS programmers to analyze and identify the root causes, and fix their HLS design to achieve better timing closure. Recent efforts have aimed to address these issues by employing coarse-grained floorplanning and pipelining strategies on task-parallel HLS designs where multiple tasks run concurrently and communicate through FIFO stream channels. However, many applications are not streaming friendly and many existing accelerator designs heavily rely on buffer channel based communication between tasks.In this work, we take a step further to support a task-parallel programming model where tasks can communicate via both FIFO stream channels and buffer channels. To achieve this goal, we design and implement the PASTA framework, which takes a large task-parallel HLS design as input and automatically generates a high-frequency FPGA accelerator via HLS and physical design co-optimization. Our framework introduces a latency-insensitive buffer channel design, which supports memory partitioning and ping-pong buffering while remaining compatible with vendor HLS tools. On the frontend, we provide an easy-to-use programming model for utilizing the proposed buffer channel; while on the backend, we implement efficient placement and pipelining strategies for the proposed buffer channel. To validate the effectiveness of our framework, we test it on four widely used Rodinia HLS benchmarks and two real-world accelerator designs and show an average frequency improvement of 25%, with peak improvements of up to 89% on AMD/Xilinx Alveo U280 boards compared to Vitis HLS baselines.